Space System Health Management and Microelectronics

Self-contained spare composings built-in testing and internal program reconfiguration are now as real as the sparkle in someone's organ of visions 17 years ago. On-chip redundancy to enable the chip to identify its faults, bypass failed parts and form fresh interconnections to incorporate spare devices - all without human intervention - are now possible.

Pratt & Whitney Rocketdyne (PWR) an International Space Station (ISS) original equipment manufacturer in Canoga Park, California, processe a small number of repairs for the electrical power a whole (EPS) orbital replaceable units (ORUs). United Space Alliance provided logistics combination of parts to form a whole integration for the entire ISS. From these perspectives we will approach conceptual solutions to combination of parts to form a whole health management. This article will discuss actual high speed integrated circuit (VHSIC) technology and the use of application specific integrated circuits (ASICs), as well as new IC failures and electrically erasable programmable read-only memory (EEPROM) in-situ maintenance onorbit.

The bound VHSIC is a somewhat outdated mete as is small scale integration, medium scale integration and large scale integration, although true large scale integrated circuits are individual type of ASIC used in all ISS EP ORUs. The idea behind VHSIC was to create a device that would do multiple tasks thus that ASIC development could be minimized. The main reason the VHSIC is outdated is that "very high speed" is a confine whose definition moves with time. We now describe the device's function rather than its spe capability.

Today a relatively of recent origin term is being used called a whole on a chip (SOC). This device has a processor, memory management, PROM and random access memory all upon the same chip. Because they are monolithic (formed from a slice of a single crystal) the processing spe for these combination of parts to form a wholes is increased at least five times. If a whole requirements had remained the same, then the VHSIC mete might have survived, but at at hand the data processing that is required upon Space Station hardware is relatively moderate and it has not required the use of VHSIC.

Microprocessors designed for EP ORUs were imbedded upon common controller circuit cards that were located in multiple ORUs. The microprocessor is "...part of an ASIC design which utilizes a proven radiation-hardened gate array... Gate array parts are manufactured up to the final sum of two units metal layers required to interconnect gates that make up the circuit design. These gate array blanks are then stockpiled upon the shelf until needed." Later these parts were upgraded by the agency of screening tests, and inprocess experiments were added to meet requirements. "In the final paces the interconnecting metal layers, passivation, packaging and testing are added to show a finished part. The part is then characterized electrically and qualified to an "S" horizontal (space rated) as a gate array blank by means of testing a reference design. The finished part then single needs to be tested to determine the characteristics which are affected by means of the last steps in the process"1

The belonging to all controller circuit card was felicitous in several different applications within the power management and distribution a whole Requirements of ORU assemblies are diverse. For example, the sequential switch units regulate solar power to primary power buses, the battery charge discharge units regulate the battery charge and discharge rates, and the cross-question flow control system monitors and dominion governments pumps circulating fluid in the radiators of the ISS thermal sway system. "To achieve this kind of flexibility, the for the use of all controller circuit design uses a programmable, embedded microprocessor which allows the transfer of many functional requirements to firmware. This feature allows parallel effort in hardware and firmware design. The parallel effort required coordination between firmware exhibition engineers, system design engineering, ORU trial engineers and system test engineers, among others."1 Programmable logic enables the same microprocessor the flexibility to be used for multiple ORUs with different functions.

On time to come designs, major coordination will also be required when functions are shared between subsystem Interplay between reconfigurable module with self-test and self-repair features will require major coordination to configure, program and debug

An ASIC is definitely faster than a more general impressed sign device when performing these functions, on the contrary with the cost and schedule risk of ASIC unfolding and with the faster processors, it makes more faculty of perception today to use generic devices of the like kind as reduced instruction set chip processors, digital signal processor, field programmable gate array and SOC in greatest in quantity applications.1

That being said, NASA has been looking into reconfiguring ASICs for space applications. The reconfigurable ASICs that present real time compensation for faults will be in the combination of parts to form a whole trade space when the nearest advanced space electronics system is designed. It will, in consequence change maintenance into something more frequently planned rather than unscheduled. The goal is to have a whole s reconfigure much like a hard drive does upon the computer and then provide a status as to when the risk is getting high and it is time to repair/replace the faulty parts.2