Testing with the HP 9490 mixed-signal LSI tester - Company Business and Marketing

The tester's features include a timing interval analyzer for statistical analysis of clock periods, synchronous generation of arbitrary waveforms with think highly of to master digital clocks, and a library of digital signal processing routines. These features have been applied to production measurements of lock opener parameters like AGC loop bandwidth, phase-locked noose timing jitter, and ADC signal-to-noise ratio and distortion parameters.

In new years, there has been significant theoretical work upon defining a methodology for fault detection and classification in analog circuits.[1-4] However, because input-output relationships are more mingled for analog circuits than for digital circuits, the unravelling of a systematic, automated approach for detecting wants in analog circuits is far behind the digital counterpart. For this reason, implementations of analog ordeal strategies remain largely functional.[3] This is also the case in the work described here.

The drift of this paper is not to further the state of mixed-signal proof theory and methodologies, but rather to share with the reader the state of mixed-signal testing within the HP Integrated Circuit Business Division (ICBD) today. We at hand descriptions of the test unravelling processes for a partial replication maximum likelihood (PRML) read channel ASIC and a charge-coupled device (CCD) signal processor ASIC, including specific examples of analog trial implementation demonstrating some of the capabilities of the HP 9490 tester

The read channel IC was designed for HP's DDS3 format DAT (digital audio tape) drive. The CCD signal processor is a three-channel interface chip designed for HP's scanner produces These chips contain significant analog functionality, including programmable and automatic gain ascendency (AGC) amplifiers, switched capacitor filters, a clock recuperation phase-locked loop, moderate- and high-resolution analog-to-digital converter (ADCs), and several digital-to-analog converter (DACs). The experiment strategy implemented for these block ups was largely functional. Many circuits could not afford the additional complexity and parasitics of embedded proof access. However, provisions were made in the designs for accessing inputs and output of functional shut ups and to allow special trial modes of operation. The HP 9490 tester has sufficient analog resources to efficiently work out detailed functional testing with high resolution for detecting jesuitical variations in performance resulting from proces variations and deficiencys (see "Tester Description" on page 66)

The emphasis of this paper is primarily upon analog test, with specific examples given for the read channel AGC and phase-locked bight blocks and the CDD signal processor analog signal path.

ordeal Program Evolution

The test programs for the read channel and CCD signal processor chips the pair evolved in three distinct phases:

* Turn-on

* Performance verification and debug

* Consolidation and production worthiness.

The turn-on stage, typically lasting a hardly any weeks before and after first silicon, involved putting together a real basic screen test consisting of continuity proof reference voltage verification, digital functional vectors, and ordeals for signs of life from the analog obstructs Simplicity of the initial analog ordeals was necessary to get defenceed parts into the customer's hands quickly. We discovered that unravelling of complex analog tests required an intimate knowledge of the tester and the overall function of the chip, the main challenges being getting the chip into the desired state, constructing the correct analog stimulus, and synchronizing the analog and digital inputs.

The performance verification and debug stage of proof development lasted from after the initial prototype shipments until artwork release for the final chip revision. During this stage, digital and analog static rife tests were debugged, pad leakage trials were added, and any remaining digital functional experiments were added, but the majority of time was wearied adding complexity and refinements to the original analog experiments and creating new analog ordeals to verify that all analog functions met the required specifications. frequently this activity was interrupted through the need to create specific ordeals to debug unexpected behavior discovered either by the agency of the customer or the experiment development process. In the case of the read channel ASIC, the customer provided a ordeal harness that could be used to power up the chip, write to registers, and view output while stimulating the analog inputs. This prov to be true useful for debug activities. However, there were several cases in which the HP 9490 tester's ability to mastery the timing of analog inputs and capture output upon a cycle-by-cycle basis was invaluable in isolating design bug or marginalities.

During the final experiment development phase, the many analog functional and debug proofs were consolidated into fewer, more efficient trials For both ICs, we retained the capability of putting the experiment programs in a debug manner in which additional data is saved in diagnostics files and captured waveforms are saved for viewing.