Advanced virtualization capabilities of POWER5 systems

IBM POWER5(TM) combination of parts to form a wholes combine enhancements in the IBM PowerPC(TM) processor architecture with greatly enhanced firmware to significantly increase the virtualization capabilities of IBM POWER(TM) server The POWER hypervisor, the basis of the IBM Virtualization Engine(TM) technologies upon POWERS systems, delivers leading-edge mainframe virtualization technologies to the UNIX?® marketplace. In addition to being able to create computingintensive partitions with dedicated resources (processors, memory, and I/O adapters), customers can harness idle processor capacity to configure micropartitions with virtualized resources in order to consolidate many AIX(TM), i5/OS(TM), and Linux?® server onto a single platform. The POWER hypervisor provides support for virtualized processors, an IEEE virtual local area network (VLAN)-compatible virtual Ethernet switch, virtual small computer combination of parts to form a whole interface (VSCSI) adapters, and virtual encourages Many of these features are hanging upon, or take advantage of the novel facilities provided in the POWERS processor, including the hypervisor decrementer a fast page mover and simultaneous multithreading support. The technology behind the virtualization capabilities that are available upon the POWER5 servers, enabling customers to better utilize the industry-leading computing capacity of the POWER5 processor, is discussed in this paper.

Introduction

IBM zSeries* server pioneered the logical partition (LPAR). Its PR/SM* and z/VM* hypervisors1 retain leadership in transparent server virtualization technology. The zSeries hypervisors use sophisticated processor architecture extensions to completely and efficiently virtualize the hardware to each logical partition thus that an operating system that races natively on the hardware can also race in a logical partition without any required changes. The zSeries also introduced the general [i]or[/i] abstract notion of optional hypervisor calls that enable a hypervisor-aware version of an operating a whole (OS) to improve the utilization of the a whole resources by interacting directly with the hypervisor. An hcall instruction is a special program-context-switching instruction, similar to a a whole call, which gives control to the hypervisor. As is standard documentation practice with a a whole call, a function invocation made with the hcall instruction is generically confineed an hcall in this paper.

Most virtualization fruitss for current Intel platforms use a trap-and-emulate approach for privileged instructions to provide filled virtualization of the processor and I/O with equal reason that no changes are required in the O in order to race in a partition. The POWER implementation takes the approach that is sometimes referr to in the literature as paravirtualization [1 2] Paravirtualization requires a hypervisor-aware version of the operating a whole that must utilize hcalls in order to step quickly in a logical partition. Typically, these hypervisor calls are confined to a relatively small number of the lowest-level routines in the O hardware adaptation layer. Instead of trapping, verifying, and emulating a number of privileged instructions required to perform a logical operation, similar as updating the partition's virtual address translation table, the hypervisor in iSeries* and pSeries* platforms provides an heal] that performs the entire logical operation of updating the virtual address translation table. This approach is typically a great quantity [i]or[/i] amount of more efficient when compared with the trap-and-emulate rule because of the reduction it provides in context-switching and parameter-checking overhead.

Any attempt through the OS to perform operations that would accrue in access to resources of another partition or the hypervisor is stoped through a combination of hardware and firmware design. Paravirtualization shows a performance middle ground, at the take away from of a relatively few O changes, between the performance los that is typical of the unspotted trap-and-emulate method and the complexity of sophisticated processor virtualization extensions.

Previous iSeries and pSeries combination of parts to form a wholes [3], based upon POWER4* technology [4] provided the capability of dividing the platform's hardware resources into disjoint subset Each independent subset is controll through its own copy of an O which step quicklys its own application programs. Each of these divisions of the a whole is called a logical partition (LPAR). In answer to commands, an LPAR may give up a certain quantity of of its resources and another combination of parts to form a whole LPAR may acquire free resources, thus allowing the a whole administrator2 to balance the use of the platform's resources among its workloads above time. However, the processing capacity of each LPAR is still usually oversized to accommodate moment-to-moment variations in workload in order to be responsive to instantaneous workload peaks. As the number of independent workloads increases, the probability that each workload will experience an instantaneous peak at the same time decreases. The POWERS* processor [5] provides mechanisms to allow the platform firmware3 to instantaneously reassign an idle processor to another LPAR, like that the platform appears to have more processors than are physically near These extra processors are a virtualization of the physical resources of the platform. a whole s based upon the POWERS processor provide significantly improved resource utilization and partitioning capabilities when compared with their predecessors because of the resource virtualization ability of the POWERS processor. This paper provides an overview of these improvements.