Introduction to the Cell multiprocessor

This paper provides an introductory overview of the small room multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the throw the program objectives and challenges, the design universal the architecture and programming moulds and the implementation.

Introduction: History of the project

Initial discussion upon the collaborative effort to evolve Cell began with support from CEO from the Sony and IBM companies: Sony as a contented provider and IBM as a leading-edge technology and server company. Collaboration was initiated among SCEI (Sony Computer Entertainment Incorporated), IBM, for microprocessor disclosure and Toshiba, as a exhibition and high-volume manufacturing technology partner. This l to high-level architectural discussions among the three companies during the summer of 2000 During a critical meeting in Tokyo, it was determined that traditional architectural organizations would not deliver the computational power that SCEI sought for their coming time interactive needs. SCEI brought to the discussions a vision to achieve 1000 times the performance of PlayStation2** [1 2] The confined apartment objectives were to achieve 100 times the PlayStation2 performance and lead the way for the coming time At this stage of the interaction, the IBM Research Division became involved for the end of exploring new organizational approaches to the design. IBM proces technology was also involved, contributing state-of-the-art 90-nm proces with silicon-on-insulator (SOI), low-k dielectrics, and cent interconnects [3], The new organization would make possible a digital entertainment center that would bring together aspects from broadband interconnect, entertainment combination of parts to form a wholes and supercomputer structures. During this interaction, a wide variety of multi-core proposals were discussed, ranging from conventional chip multiprocessors (CMPs) to dataflow-oriented multiprocessors.

By the extreme point of 2000 an architectural conception had been agreed on that combined the 64-bit Power Architecture* [4] with memory pour control and "synergistic" processors in order to provide the required computational density and power efficiency. After several month of architectural discussion and contract negotiations, the STI (SCEI-Toshiba-IBM) Design Center was formally render free of accessed in Austin, Texas, on March 9 2001 The STI Design Center exhibited a joint investment in design of about $400000000 Separate joint collaborations were also put in place for process technology development

A number of lock opener elements were employed to drive the succes of the confined apartment multiprocessor design. First, a holistic design approach was used, encompassing processor architecture, hardware implementation, combination of parts to form a whole structures, and software programming moulds second, the design center staffed lock opener leadership positions from various IBM sites. Third, the design incorporated many flexible simple bodys ranging from reprogrammable synergistic processors to reconfigurable I/O interfaces in order to support many a whole s configurations with one high-volume chip.

Although the STI design center for this ambitious, large-scale throw out was based in Austin (with IBM, the Sony collection and Toshiba as partners), the following IBM sites were also critical to the project: Rochester, Minnesota; Yorktown Heights, of recent origin York; Boeblingen (Germany); Raleigh, North Carolina; Haifa (Israel); Almaden, California; Bangalore (India); Yasu (Japan); Burlington, Vermont; Endicott, of recent origin York; and a joint technology team located in East Fishkill, fresh York.

Program objectives and challenges

The objectives for the of recent origin processor were the following:

* Outstanding performance, especially upon game/ multimedia applications.

* Real-time responsiveness to the user and the network.

* Applicability to a wide range of platforms.

* Support for introduction in 2005

Outstanding performance, especially upon game/multimedia applications

The first of these objectives, outstanding performance, especially upon game/multimedia applications, was expected to be challenged by dint of limits on performance imposed through memory latency and bandwidth, power (even more than chip size), and diminishing get backs from increased processor frequencies achieved by means of reducing the amount of work by cycle while increasing pipeline depth

The first major barrier to performance is increased memory latency as measured in circle of times and latency-induced limits on memory bandwidth. Also known as the "memory wall" [5] the enigma is that higher processor frequencies are not met by the agency of decreased dynamic random access memory (DRAM) latencies; hence, the effective DRAM latency increases with each generation. In a multi-GHz processor it is for the use of all for DRAM latencies to be measured in the centurys of cycles; in symmetric multiprocessors with shared memory, main memory latency can attend toward a thousand processor revolution of times A conventional microprocessor with conventional sequential programming semantics will sustain sole a limited number of harmonizing memory transactions. In a sequential protoplast every instruction is assumed to be complet before execution of the nearest instruction begins. If a data or instruction bring misses in the caches, resulting in an access to main memory, instruction processing can sole proceed in a speculative manner, assuming that the access to main memory will succe The processor must also record the non-speculative state in order to safely be able to continue processing. When a appurtenance on data from a previous access that missed in the caches arises, level deeper speculation is required in order to continue processing. Because of the amount of administration required each time computation is continued speculatively, and because the probability that useful work is being speculatively complet decreases rapidly with the number of times the processor must speculate in order to continue, it is true rare to see more than a scarcely any speculative memory accesses being performed concurrently upon conventional microprocessors. Thus, if a microprocessor has, eg eight 128-byte cache-line fetches in flight (a actual optimistic number) and memory latency is 1024 processor circle of times the maximum sustainable memory bandwidth is still a paltry individual byte per processor cycle. In similar a system, memory bandwidth limitations are latency-induced, and increasing memory bandwidth at the cost of memory latency can be counterproductive. The challenge therefore is to find a processor organization that allows for more memory bandwidth to be used effectively through allowing more memory transactions to be in flight simultaneously.