evolution of build-up package technology and its design challenges, The

This paper reviews sequential build-up (SBU) laminate substrate unfolding from its beginning in 1988 It reports upon developments in this technology for IBM applications since its adoption in 2000 These laminated substrates are nonuniform manner of makings composed of three elements: a core, build-up layers, and finishing layers. Each ultimate part has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology true suitable for high-performance designs. This paper focuses upon the challenges encountered by IBM during the design, manufacture, and reliability testing phases of disclosure of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.

Introduction

The increasing demand for computer performance has l to higher chip internal clock frequencies and parallelism, and has increased the ne for higher bandwidth and lower latencies. Processor frequencies are predicted to reach 29 GHz by means of 2018, and off-chip signaling interface make hastes are expected to exceed 56 Gb/ [1 2] Optimization of bandwidth, power, pin enumerate or number of wires and require to be paid [i]or[/i] undergone are the goals for high-speed interconnect design. The electrical performance of interconnects is restricted by the agency of noise and timing limitations of the silicon, package, board and cable.

As a issue of rapidly emerging technologies and applications, the boundaries between semiconductor, packaging, and combination of parts to form a whole technologies are no longer clear; they must all be considered concurrently in a system-level approach in order to optimize the substrate design. There is an increased awareness in the semiconductor industry that assembly and packaging is an essential and integral part of the semiconductor proceeds Packaging technology has become a critical competitive factor in many market sections since it affects operating oftenness power, reliability, and cost.

Sequential build-up (SBU) laminate substrate technology is now the technology of choice for highdensity, high-performance silicon packaging. In 1997 SBU technology was picked by Intel [3] for flipchip packaging and has been widely adapted for this application. This paper reviews the invention of laminate substrate packaging and discusses rapidly evolving runs in the evolution of SBU including its broadening application in IBM server for high-speed system-level interconnects. The importance of suitably designing the substrate for high-speed signaling is discussed, including identification of lock opener parameters and design tradeoffs for one as well as the other application-specific integrated circuit (ASIC) and microprocessor chip designs.

Applications place performance demands upon packaging which can best be met by means of organic materials. The key attributes of organic laminate package technologies as they pertain to the electrical performance of the subassembly are highly electrically conductive metallurgy to minimize resistive voltage globules and to effectively deliver power to the chip; low-inductance connections to bring simultaneous switching noise; low-dielectricconstant insulator materials to better match board impedances and to restore undesirable parasitic capacitances; and advanced thermal interface materials to manage high power densities upon the chip and to improve performance. The importance of suitably designing the substrate for these applications is emphasized, including a discussion of the identification and rule of key physical design parameters and a description of the design optimization technique.

History of technology development

Technology origins

Wire-bond interconnects have been the workhorse technology [4] for industry microprocessors and their associated supporting chips since the inception of the personal computer industry. Its primary advantages have been depressed cost, design flexibility, and thoroughly demonstrated reliability. Its major limitation is wiring capability in metes of both total numbers of signals and electrical performance.

Flip-chip interconnection has been a core IBM approach to silicon packaging [5] for abundant of the history of IBM server It provides the highest interconnect density from a chip to redistribution circuitry, or substrate, that is publicly possible. Until recently, the interconnect density enabled by means of flip-chip technology could be provided sole by multilayer ceramic substrates, which have a manufacturing require to be paid [i]or[/i] undergone significantly higher than that of other packaging circuit ultimate parts of a system, such as printed circuit boards (PCBs) Analysis of published design mould rules shows that build-up laminate substrate technology is a breakthrough approach to flipchip interconnection, achieving significantly higher perlayer wiring densities than printed circuit boards that use many of the same basic materials and processe Build-up laminate take away from is significantly less than that of ceramic dielectric-based competitive technologies. It presents electrical performance enhancements as well from one side the use of copper conductors and lower-dielectric-constant insulator materials.