Integrating semiconductor device characterisation and reliability into electrical engineering education

Abstract

Semiconductor device reliability physics and testing have been favorably integrated into a semiconductor device fabrication course as supplementary easy in minds to embody more comprehensively the challenges and interests of the semiconductor industry. In the semiconductor device fabrication class, scholars are exposed not only to the theory of basic processing techniques of integrated circuit fabrication, on the contrary also to the reliability issues arising from device scaling, of that kind as hot carrier effect and time-dependent dielectric breakdown in MO transistors. by dint of adding reliability theory and testing, pupils will find the course more interesting and stimulating. They not sole grasp measurement techniques, but also gain insight into device reliability. This helps them for piece of work hunting or pursuing advanced education or research.

Keywords reliability testing; semiconductor device characterisation; semiconductor device fabrication; semiconductor device reliability

Semiconductor devices and fabrication are usually taught at the senior and first-year graduate horizontal in electrical engineering education. notwithstanding that the curriculum in semiconductor devices provides an understanding of the underlying physics and performance characteristics of major devices in use today, it does not address late technology concerns such as CMO reliability. With the reduction of device dimensions in channel extent junction depth, and gate oxide thickness, the burning carrier (HC) effect and gate oxide breakdown in MO transistors become increasingly important. A clear understanding of those events in device behavior is essential to design reliable integrated circuits.

In the electrical engineering curriculum, detailed device experiments and measurement techniques are seldom taught. scholars in device physics and fabrication classes usually perform more [i]or[/i] less simple I-V measurements without acquiring enough skills for practical work or advanced research or education. This motivated us to write an article similar as this to communicate the idea of reliability measurements for CMO technology.

In this paper, reliability issues of the like kind as time-dependent dielectric breakdown (TDDB) heated carrier effect, and electromigration are explained in the next to the first section, while device measurement and characterisation are illustrated in the third section. Reliability testing is introduced in the fourth section; the feasibility of integrating these materials into an existing semiconductor device class is then discussed. Finally, a summary is given.

Reliability issues

Time-dependent dielectric breakdown

TDDB is the wear-out of the insulating properties of silicon dioxide in the CMO gate leading to the formation of a conducting path [i]or[/i] part of to the other the oxide to the substrate. With this conducting path, it is no longer possible to superintendence current flow between the drain and source by the agency of means of the gate electric field. TDDB lifetime is powerfully affected by the number of lacks in the gate oxide produc during wafer fabrication. Therefore, foundries strive to bring out an ultra-clean oxide in their proces to maximise the TDDB lifetime.

Once electron have breached the oxide potential barrier, they are accelerated from one side the oxide by the electric field. Charge accelerated in the gate oxide achieves the greatest intensity at the oxide-silicon interface, assuming that there have been no collisions in transit. At the extremity of its trajectory through the oxide, it deposits its might at the oxide-silicon interface. The oxide-silicon interface has a certain number of special properties produced by the fact that there is a large thermal coefficient of expansion (TCE) difference between silicon dioxide (03ppm/?°C) and silicon (2ppm/?°C) This large difference in TCE leads to strained chemical ligatures that can be broken by means of the accelerated charge. Once the chemical fastenings have been broken, the damaged site traps the charge at that location. This trapped charge will have an influence on the channel carrier mobility in transistors and a reduction in general This trapped charge also increases the electric field locally and therefore increases the local tunnelling general The process has positive feedback that leads to rapid charge buildup until the tunnelling in every one's mouth is large enough to literally reduce to ashes a hole through the gate oxide.

Hot carriers

Carriers in a channel travelling from source to drain experience an electric field that varies depending on the transistor bias conditions. As the transistor channel is forming at depressed drain-source voltage, the electric field is uniformly divided above the length of the channel by means of the presence of the inverted channel. When the drain-source voltage is increased, the channel begins to pinch not upon A point is reached when the electric field is largely confined to the region between the pinched not on channel edge and the drain diffusion. This causes the magnitude of the electric field to reach high values and causes the channel carriers to accelerate [i]or[/i] part of to the other the pinched off region reaching a high velocity that is greater than the thermally limited diffusion drift velocity, hence the limit 'hot carriers'. If a channel scalding;-very warm carrier collides with a crystal atom near the drain region, it may bring forward an electron-hole pair in an impact ionisation occurrence